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| DM74AS646 * DM74AS648 Octal Bus Transceiver and Register October 1986 Revised March 2000 DM74AS646 * DM74AS648 Octal Bus Transceiver and Register General Description This device incorporates an octal bus transceiver and an octal D-type register configured to enable multiplexed transmission of data from bus to bus or internal register to bus. This bus transceiver features totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance third state and increased high-logic-level drive provide this device with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. It is particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The registers in the DM74AS646, DM74AS648 are edgetriggered D-type flip-flops. On the positive transition of the clock (CAB or CBA), the input bus data is stored. The SAB and SBA control pins are provided to select whether real-time data or stored data is transferred. A LOW input level selects real-time data, and a HIGH level selects stored data. The select controls have a "make before break" configuration to eliminate a glitch which would normally occur in a typical multiplexer during the transition between stored and real-time data. The enable G and direction control pins provide four modes of operation; real-time data transfer from bus A to B, realtime data transfer from bus B to A, real-time bus A and/or B data transfer to internal storage, or internal store data transfer to bus A or B. When the enable G pin is LOW, the direction pin selects which bus receives data. When the enable G pin is HIGH, both buses become disabled yet their input function is still enabled. Features s Switching specifications at 50 pF s Switching specifications guaranteed over full temperature and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL process s Functionally and pin-for-pin compatible with LS TTL counterpart s 3-STATE buffer-type outputs drive bus lines directly Ordering Code: Order Number DM74AS646WM DM74AS646NT DM74AS648WM DM74AS648NT Package Number M24B N24C M24B N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. (c) 2000 Fairchild Semiconductor Corporation DS006324 www.fairchildsemi.com DM74AS646 * DM74AS648 Connection Diagram Function Table Inputs G H L L DIR X X L L H H X X X X CAB X X X H or L X CBA X H or L X X X Data I/O (Note 1) SAB SBA A1 thru A8 B1 thru B8 X X X X L H X X X X L H X X X X Input Unspecified (Note 1) Input Output Output Input Input Input Operation or Function DM74AS646 Isolation, Hold Storage Store A and B Data Stored B Data to A Bus Stored A Data to B Bus Unspecified Store A, B Unspecified (Note 1) (Note 1) Input Store B, A Unspecified (Note 1) DM74AS648 Isolation, Hold Storage Store A and B Data Stored B Data to A Bus Stored A Data to B Bus Store A, B Unspecified (Note 1) Store B, A Unspecified (Note 1) H or L H or L Real Time B Data to A Bus Real Time B Data to A Bus Real Time A Data to B Bus Real Time A Data to B Bus H--HIGH level; L--LOW level; X--irrelevant; --LOW-to-HIGH level transition Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. www.fairchildsemi.com 2 DM74AS646 * DM74AS648 Logic Diagrams (positive logic) DM74AS646 DM74AS648 Different Modes of Control for DM74AS646, DM74AS648 Storage From A, B or A and B Transfer Stored Data to A or B (Note 2) Real-Time Transfer Bus A to Bus B (Note 2) Real-Time Transfer Bus B to Bus A (Note 2) Note 2: The complement of A and B data are stored and transferred for DM74AS648 3 www.fairchildsemi.com DM74AS646 * DM74AS648 Absolute Maximum Ratings(Note 3) Supply Voltage Input Voltage Control Inputs I/O Ports Operating Free Air Temperature Range Storage Temperature Range Typical JA N Package M Package 41.1C/W 81.5C/W 7V 5.5V 0C to +70C -65C to +150C Note 3: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. 7V Recommended Operating Conditions Symbol VCC VIH VIL IOH IOL fCLK tW tSU tH TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency Width of Clock Pulse Data Setup Time (Note 4) Data Hold Time (Note 4) Free Air Operating Temperature HIGH LOW 0 5 6 6 0 0 70 Parameter Min 4.5 2 0.8 -15 48 90 Nom 5 Max 5.5 Units V V V mA mA MHz ns ns ns ns C Note 4: The () arrow indicates the positive edge of the Clock is used for reference. Electrical Characteristics over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25C. Symbol VIK VOH Parameter Input Clamp Voltage HIGH Level Output Voltage VOL II IIH IIL IO ICC LOW Level Output Voltage Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Output Drive Current Supply Current (Note 5) VCC = 5.5V, VIL = 0.4V (Note 5) VCC = 5.5V, VO = 2.25V VCC = 5.5V DM74AS646 Outputs HIGH Outputs LOW Outputs Disabled Outputs HIGH DM74AS648 Outputs LOW Outputs Disabled Note 5: For I/O ports, the parameters IIH and IIL include the OFF-State current, IOZH and IOZL. Conditions VCC = 4.5V, II = -18 mA VCC = 4.5V, VIL = Max VIH = Min VCC = 4.5V, VIL = Min VIH = 2V, IOL = Max VCC = 5.5V VI = 7V VI = 5.5V VCC = 5.5V, VIH = 2.7V Control Inputs A or B Ports Control Inputs A or B Ports Control Inputs A or B Ports IOH = Max IOH = -3 mA Min Typ Max -1.2 Units V V 2 2.4 VCC - 2 0.35 0.5 0.1 0.1 20 70 -0.5 -0.75 -30 120 130 130 110 120 120 -112 195 211 211 185 195 195 mA V mA A mA mA 3.2 VCC = 4.5V to 5.5V, IOH = -2 mA www.fairchildsemi.com 4 DM74AS646 * DM74AS648 DM74AS646 Switching Characteristics Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Parameter Maximum Clock Frequency Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Output Enable Time to HIGH Level Output Output Enable Time to LOW Level Output Output Disable Time from HIGH Level Output Output Disable Time from LOW Level Output Output Enable Time to HIGH Level Output Output Enable Time to LOW Level Output Output Disable Time from HIGH Level Output Output Disable Time from LOW Level Output Note 6: These parameters are measured with the internal output state of the storage register opposite to that of the bus input. Conditions VCC = 4.5V to 5.5V, R1 = R2 = 500 CL = 50 pF From (Input) To (Output) Min 90 2 Max Units MHz 8.5 9 9 7 11 9 9 14 9 9 16 18 10 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns CBA or CAB A or B 2 2 A or B B or A 1 2 SBA or SAB (Note 6) A or B 2 2 3 Enable G A or B 2 2 3 3 DIR A or B 2 2 5 www.fairchildsemi.com DM74AS646 * DM74AS648 DM74AS648 Switching Characteristics Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Parameter Maximum Clock Frequency Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Output Enable Time to HIGH Level Output Output Enable Time to LOW Level Output Output Disable Time from HIGH Level Output Output Disable Time from LOW Level Output Output Enable Time to HIGH Level Output Output Enable Time to LOW Level Output Output Disable Time from HIGH Level Output Output Disable Time from LOW Level Output Note 7: These parameters are measured with the internal output state of the storage register opposite to that of the bus input. Conditions VCC = 4.5V to 5.5V, R1 = R2 = 500 CL = 50 pF From (Input) To (Output) Min 90 2 Max Units MHz 8.5 9 8 7 11 9 9 15 9 9 16 18 10 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns CAB or CBA A or B 2 2 A or B B or A 1 2 SBA or SAB (Note 7) A or B 2 2 3 Enable G A or B 2 2 3 3 DIR A or B 2 2 www.fairchildsemi.com 6 DM74AS646 * DM74AS648 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 7 www.fairchildsemi.com DM74AS646 * DM74AS648 Octal Bus Transceiver and Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com |
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